VHDL

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-- 0001 VHDL - Multiplexer, Halfadder, Fulladder, Paralleladder, Coder, Decoder
-- without architecture and entity - this will be in 0002 - VHDL

-- Multiplexer 

    signal a: bit_vector (3 downto 0);
    signal b: bit_vector (3 downto 0);
    signal c: bit_vector (3 downto 0);
    
    process (cout)
    begin
        a <= ain;
        b <= bin;
        if (clk='0') then
            c <= a;
        elseif (clk='1') then
            c <= b;
        end if;
        cout <= c;
    end process;
            
-- Adder

    signal a: bit;
    signal b: bit;
    signal c: bit;
    signal s: bit;
    
    process (cout, sout)
    begin
        a <= ain;
        b <= bin;
        c <= a xor b;
        s <= a and b;
        cout <= c;
        sout <= s;
    end process;

-- Fulladder 

    signal a: bit;
    signal b: bit;
    signal c: bit;
    signal s0: bit;
    signal s1: bit;
    
    process (cout, sout)
    begin
        a <= ain;
        b <= bin;
        s0 <= sin;
        
        c <= a xor b xor s0;
        s1 <= (a and b) or (a or b) and c;
        
        cout <= c;
        sout <= s1;
    end process;