Code: Alles auswählen
lb, lbu: Load a byte
lh, lhu: loading a half word
lw, ld*
la*, li*
lw loading a word
ld* load a double word
la*: Loading an address
li*: Loading an immediate value
sb, sh, sw, sd*
sb: Save a byte
sh: storing a half word
sw: Save a word
sd*: Save a double word
Data movement commands
Arithmetic Logical Instructions
Slide and rotate commands
Multimedia commands
Floating point instructions
Program control instructions
System control commands
Stack architecture: 8087 Intel ATAM862 Atmel
Stack and cellar architecture
Accumulator architecture
Memory-memory architecture
Register memory memory architecture
Register-register architecture
Data format:
Integer
Single bit
floating point
multimedia
f=(-1)^s*1.m*2^(e-b)
32-bit single precision
64-bit double precision
80-bit advanced accuracy
IEEE 754 standard
Direct value addressing
Immediate addressing
Direct addressing
Indirect addressing
Indexed addressing
Indirect addressing with auto increment/decrement
Indirect addressing with displacement
Indexed addressing with displacement
MemToReg
MemWrite
Branch
ALU Src
RegDst
RegWrite
ALU Op
Command decoder
Function decoder
ALU
Register set
Data storage
Instruction memory
Command counter
1 x AND
2 x MUX
2 x adder numbers
2 x 4 bit shifters
ALU Src
ALU Op
Aluminum operands
ALU inputs:
- Input register
- Zero
Register set
- Data input register 1
- Data input register 2
- An exit
ALU-Src ALU-Op ALU operands
00 010 - add
x1 110 - sub
1x 010 - add
R type 000000 1 1 0 0 0 0 10
1.) Conditional
2.) Absolutely
- eq - eual
- no - not equal
- ge - greater then equal
- gt - greater than
- lt - less than
- le - less than equal
yes - jump if above
jal - jump and link
beq, bne
beqz*, bnez*
ble, ble
bltz, blez
bgt, bge
bgtz, bz
1.) Static command scheduling
2.) Dynamic
VLIW - Very Long Instruction Word Processor
1.) Static
- In Order Issue In Order Completio
2.) Dynamic
- Out Of Order Issue Out Of Order Completion
1.) Predict always not taken
2.) Predict Always Taken
3.) Predict backward taken, forward not taken
1 and 2 bit predictor
1.) T -> NT, NT->T
2.) Predict Strongly Taken, Predict Weakly Taken, Predict weakly Not Taken, Predict strongly not taken