Re: VHDL-Übung

entity meineschaltung is
port
(
    a: in bit_vector (3 downto 0);
    b: in bit_vector (3 downto 0);
    c: out bit_vector (3 downto 0)
);
end;

architecture behaviour of meineschaltung is
begin
    c(3) <= a(3) and b(3);
    c(2) <= a(2) and b(2);
    c(1) <= a(1) and b(1);
    c(0) <= a(0) and b(0);
end;