b a x b a y 0 0 0 0 1 0 0 1 0 0 1 1 1 1 2 0 1 0 0 0 1 3 0 1 1 0 1 1 4 1 0 0 1 1 0 5 1 0 1 1 0 1 6 1 1 0 0 1 1 7 1 1 1 0 0 1 b a x b 0 0 0 0 1 1 0 0 1 1 2 0 1 0 0 3 0 1 1 0 4 1 0 0 1 5 1 0 1 1 6 1 1 0 0 7 1 1 1 0 b a x a 0 0 0 0 0 1 0 0 1 1 2 0 1 0 0 3 0 1 1 1 4 1 0 0 1 5 1 0 1 0 6 1 1 0 1 7 1 1 1 0 b a x y 0 0 0 0 0 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 0 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 b a x b 0 0 0 0 1 1 0 0 1 1 4 1 0 0 1 5 1 0 1 1 b a x a 1 0 0 1 1 3 0 1 1 1 4 1 0 0 1 6 1 1 0 1 b a x y 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 b a x b Gruppe 0: 0 0 0 0 1 Gruppe 1: 1 0 0 1 1 4 1 0 0 1 Gruppe 2: 5 1 0 1 1 b a x a Gruppe 1: 1 0 0 1 1 4 1 0 0 1 Gruppe 2: 3 0 1 1 1 6 1 1 0 1 b a x y Gruppe 1: 1 0 0 1 1 2 0 1 0 1 Gruppe 2: 3 0 1 1 1 5 1 0 1 1 6 1 1 0 1 Gruppe 3: 7 1 1 1 1 b a x b Gruppe 0: 0 0 0 0 1 Gruppe 1: 1 0 0 1 1 4 1 0 0 1 Gruppe 2: 5 1 0 1 1 0:1 0 0 - 0:4 - 0 0 1:5 - 0 1 4:5 1 0 - 0:1 0 0 - 4:5 1 0 - 0:4 - 0 0 1:5 - 0 1 0:1:4:5 - 0 - b <= not a b a x a Gruppe 1: 1 0 0 1 1 4 1 0 0 1 Gruppe 2: 3 0 1 1 1 6 1 1 0 1 1:3 0 - 1 3:6 1 - 0 a <= (not b and x) or (b and not x) a <= (b xor x) b a x y Gruppe 1: 1 0 0 1 1 2 0 1 0 1 Gruppe 2: 3 0 1 1 1 5 1 0 1 1 6 1 1 0 1 Gruppe 3: 7 1 1 1 1 1:3 0 - 1 1:5 - 0 1 2:3 0 1 - 2:6 - 1 0 3:7 - 1 1 5:7 1 - 1 6:7 1 1 - 1:3 0 - 1 5:7 1 - 1 1:5 - 0 1 2:6 - 1 0 3:7 - 1 1 2:3 0 1 - 6:7 1 1 - Gruppe 1: 1:3 0 - 1 Gruppe 2: 5:7 1 - 1 1:3:5:7 - - 1 Gruppe 1: 1:5 - 0 1 2:6 - 1 0 Gruppe 2: 3:7 - 1 1 1:5:3:7 - - 1 2:6:3:7 - 1 - Gruppe 1: 2:3 0 1 - Gruppe 2: 6:7 1 1 - 2:3:6:7 - 1 - y <= (x or a) b <= not a a <= (not b and x) or (b and not x) a <= (b xor x) y <= (x or a)
entity uebergangsschaltnetz is port ( b: inout bit; a: inout bit; x: in bit ); end; entity ausgangsschaltnetz is port ( b: in bit; a: in bit; x: in bit; y: out bit ); end; architecture verhalten of uebergangsschaltnetz is begin b <= not a; a <= (not b and x) or (b and not x); end; architecture verhalten of ausgangsschaltnetz is begin y <= (x or a); end;