b a x b a y 0 0 0 0 1 0 0 1 0 0 1 0 1 0 2 0 1 0 0 0 1 3 0 1 1 1 1 1 4 1 0 0 1 0 0 5 1 0 1 0 0 0 6 1 1 0 0 1 1 7 1 1 1 0 0 0 b a x b 0 0 0 0 1 1 0 0 1 0 2 0 1 0 0 3 0 1 1 1 4 1 0 0 1 5 1 0 1 0 6 1 1 0 0 7 1 1 1 0 b a x a 0 0 0 0 0 1 0 0 1 1 2 0 1 0 0 3 0 1 1 1 4 1 0 0 0 5 1 0 1 0 6 1 1 0 1 7 1 1 1 0 b a x y 0 0 0 0 0 1 0 0 1 0 2 0 1 0 1 3 0 1 1 1 4 1 0 0 0 5 1 0 1 0 6 1 1 0 1 7 1 1 1 0 b a x b 0 0 0 0 1 3 0 1 1 1 4 1 0 0 1 b a x a 1 0 0 1 1 3 0 1 1 1 6 1 1 0 1 b a x y 2 0 1 0 1 3 0 1 1 1 6 1 1 0 1 b a x b Gruppe 0: 0 0 0 0 1 Gruppe 1: 4 1 0 0 1 Gruppe 2: 3 0 1 1 1 b a x a Gruppe 1: 1 0 0 1 1 Gruppe 2: 3 0 1 1 1 6 1 1 0 1 b a x y Gruppe 1: 2 0 1 0 1 Gruppe 2: 3 0 1 1 1 6 1 1 0 1 b a x b Gruppe 0: 0 0 0 0 1 Gruppe 1: 4 1 0 0 1 Gruppe 2: 3 0 1 1 1 0:4 - 0 0 3 0 1 1 b <= (not a and not x) or (not b and a and x) b a x a Gruppe 1: 1 0 0 1 1 Gruppe 2: 3 0 1 1 1 6 1 1 0 1 1:3 0 - 1 6 1 1 0 a <= (not b and x) or (b and a and not x) b a x y Gruppe 1: 2 0 1 0 1 Gruppe 2: 3 0 1 1 1 6 1 1 0 1 2:3 0 1 - 2:6 - 1 0 y <= (not b and a) or (a and not x) b <= (not a and not x) or (not b and a and x) a <= (not b and x) or (b and a and not x) y <= (not b and a) or (a and not x)
entity meinausgangsschaltnetz is port ( b, a: inout bit; x: in bit ); end; entity meinuebergangsnetz is port ( b, a: in bit; y: out bit ); end; architecture verhalten of meinausgangsschaltnetz is begin y <= (not b and a) or (a and not x); end; architecture verhalten of meinuebergansgnetz is begin b <= (not a and not x) or (not b and a and x); a <= (not b and x) or (b and a and not x); end;