Nächste Seite: Re: Aufgaben und Übungen, Aufwärts: Graphen, Schaltwerke und Zahlen Vorherige Seite: Re: Aufgaben und Übungen,
0 0 0 0 0 1
1 0 0 0 1 0
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 0
6 0 1 1 0 1
7 0 1 1 1 0
8 1 0 0 0 0
9 1 0 0 1 0
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 0
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1
0 0 0 0 0 1
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 1
6 0 1 1 0 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1
Gruppe 0:
0 0 0 0 0 1
Gruppe 1:
2 0 0 1 0 1
4 0 1 0 0 1
Gruppe 2:
3 0 0 1 1 1
6 0 1 1 0 1
Gruppe 3:
13 1 1 0 1 1
14 1 1 1 0 1
Gruppe 4:
15 1 1 1 1 1
Gruppe 0:
0 0 0 0 0 1
Gruppe 1:
2 0 0 1 0 1
4 0 1 0 0 1
Gruppe 2:
3 0 0 1 1 1
6 0 1 1 0 1
Gruppe 3:
13 1 1 0 1 1
14 1 1 1 0 1
Gruppe 4:
15 1 1 1 1 1
0:2 0 0 - 0
0:4 0 - 0 0
2:3 0 0 1 -
2:6 0 - 1 0
4:6 0 1 - 0
6:14 - 1 1 0
13:15 1 1 - 1
14:15 1 1 1 -
2:3 0 0 1 -
14:15 1 1 1 -
0:2 0 0 - 0
4:6 0 1 - 0
13:15 1 1 - 1
0:4 0 - 0 0
2:6 0 - 1 0
6:14 - 1 1 0
Gruppe 1:
2:3 0 0 1 -
Gruppe 3:
14:15 1 1 1 -
Gruppe 0:
0:2 0 0 - 0
Gruppe 1:
4:6 0 1 - 0
Gruppe 3:
13:15 1 1 - 1
Gruppe 0:
0:4 0 - 0 0
Gruppe 1:
2:6 0 - 1 0
Gruppe 2:
6:14 - 1 1 0
2:3 0 0 1 -
14:15 1 1 1 -
Gruppe 0:
0:2 0 0 - 0
Gruppe 1:
4:6 0 1 - 0
Gruppe 3:
13:15 1 1 - 1
0:2:4:6 0 - - 0
13:15 1 1 - 1
Gruppe 0:
0:4 0 - 0 0
Gruppe 1:
2:6 0 - 1 0
0:4:2:6 0 - - 0
Gruppe 2:
6:14 - 1 1 0
2:3 0 0 1 -
14:15 1 1 1 -
0:2:4:6 0 - - 0
13:15 1 1 - 1
0:4:2:6 0 - - 0
6:14 - 1 1 0
2:3 0 0 1 -
14:15 1 1 1 -
0:2:4:6 0 - - 0
13:15 1 1 - 1
6:14 - 1 1 0
0 2 3 4 6 13 14 15
2:3 * *
14:15 * *
0:2:4:6 * * * *
13:15 * *
6:14 * *
0 2 3 4 6 13 14 15
2:3 * *
14:15 * *
0:2:4:6 * * * *
13:15 * *
2:3 0 0 1 -
14:15 1 1 1 -
0:2:4:6 0 - - 0
13:15 1 1 - 1
DNF:
y <= (not x3 and not x2 and x1) or
(x3 and x2 and x1) or
(not x3 and not x0) or
(x3 and x2 and x0);
KNF:
y <= (x3 or x2 or not x1) and
(not x3 or not x2 or not x1) and
(x3 or x0) and
(not x3
\section{ Re: Aufgaben und "Ubungen, Jetzt in VHDL
\section{ Re: Aufgaben und "Ubungen, }
\begin{verbatim}
0 0 0 0 0 1
1 0 0 0 1 0
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 0
6 0 1 1 0 1
7 0 1 1 1 0
8 1 0 0 0 0
9 1 0 0 1 0
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 0
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1
0 0 0 0 0 1
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 1
6 0 1 1 0 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1
Gruppe 0:
0 0 0 0 0 1
Gruppe 1:
2 0 0 1 0 1
4 0 1 0 0 1
Gruppe 2:
3 0 0 1 1 1
6 0 1 1 0 1
Gruppe 3:
13 1 1 0 1 1
14 1 1 1 0 1
Gruppe 4:
15 1 1 1 1 1
Gruppe 0:
0 0 0 0 0 1
Gruppe 1:
2 0 0 1 0 1
4 0 1 0 0 1
Gruppe 2:
3 0 0 1 1 1
6 0 1 1 0 1
Gruppe 3:
13 1 1 0 1 1
14 1 1 1 0 1
Gruppe 4:
15 1 1 1 1 1
0:2 0 0 - 0
0:4 0 - 0 0
2:3 0 0 1 -
2:6 0 - 1 0
4:6 0 1 - 0
6:14 - 1 1 0
13:15 1 1 - 1
14:15 1 1 1 -
2:3 0 0 1 -
14:15 1 1 1 -
0:2 0 0 - 0
4:6 0 1 - 0
13:15 1 1 - 1
0:4 0 - 0 0
2:6 0 - 1 0
6:14 - 1 1 0
Gruppe 1:
2:3 0 0 1 -
Gruppe 3:
14:15 1 1 1 -
Gruppe 0:
0:2 0 0 - 0
Gruppe 1:
4:6 0 1 - 0
Gruppe 3:
13:15 1 1 - 1
Gruppe 0:
0:4 0 - 0 0
Gruppe 1:
2:6 0 - 1 0
Gruppe 2:
6:14 - 1 1 0
2:3 0 0 1 -
14:15 1 1 1 -
Gruppe 0:
0:2 0 0 - 0
Gruppe 1:
4:6 0 1 - 0
Gruppe 3:
13:15 1 1 - 1
0:2:4:6 0 - - 0
13:15 1 1 - 1
Gruppe 0:
0:4 0 - 0 0
Gruppe 1:
2:6 0 - 1 0
0:4:2:6 0 - - 0
Gruppe 2:
6:14 - 1 1 0
2:3 0 0 1 -
14:15 1 1 1 -
0:2:4:6 0 - - 0
13:15 1 1 - 1
0:4:2:6 0 - - 0
6:14 - 1 1 0
2:3 0 0 1 -
14:15 1 1 1 -
0:2:4:6 0 - - 0
13:15 1 1 - 1
6:14 - 1 1 0
0 2 3 4 6 13 14 15
2:3 * *
14:15 * *
0:2:4:6 * * * *
13:15 * *
6:14 * *
0 2 3 4 6 13 14 15
2:3 * *
14:15 * *
0:2:4:6 * * * *
13:15 * *
2:3 0 0 1 -
14:15 1 1 1 -
0:2:4:6 0 - - 0
13:15 1 1 - 1
DNF:
y <= (not x3 and not x2 and x1) or
(x3 and x2 and x1) or
(not x3 and not x0) or
(x3 and x2 and x0);
KNF:
y <= (x3 or x2 or not x1) and
(not x3 or not x2 or not x1) and
(x3 or x0) and
(not x3 or not x2 or not x0);
entity meinschaltnetz0028 is
port
(
x3, x2, x1, x0: in bit;
y: out bit
);
end;
architecture verhaltendnf of meinschaltnetz0028 is
begin
y <= (not x3 and not x2 and x1) or
(x3 and x2 and x1) or
(not x3 and not x0) or
(x3 and x2 and x0);
end;
architecture verhaltenknf of meinschaltnetz0028 is
begin
y <= (x3 or x2 or not x1) and
(not x3 or not x2 or not x1) and
(x3 or x0) and
(not x3 or not x2 or not x0);
end;