entity meinschaltnetz0028 is port ( x3, x2, x1, x0: in bit; y: out bit ); end; architecture verhaltenknf of meinschaltnetz0028 is begin y <= (x3 or x2 or not x1) and (not x3 or not x2 or not x1) and (x3 or x0) and (not x3 or not x2 or not x0); end; architecture verhaltendnf of meinschaltnetz0028 is begin y <= (not x3 and not x2 and x1) or (x3 and x2 and x1) or (not x3 and not x0) or (x3 and x2 and x0); end; entity testbench is end; architecture verhalten of testbench is component meinschaltnetz0028 port ( x3, x2, x1, x0: in bit; y: out bit ); end component; signal x3, x2, x1, x0, y: bit; begin meinschaltnetz: meinschaltnetz0028 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y); x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns; x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns; x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns; x3 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns; end;