Re: Aufgaben und Übungen,

-- OK und es hat sich bewahrheitet, was ich "uber das RS-Latch sagte, wenn man nicht bit verwendet, sondern std_logic, dann wird es bei 0, 0 nicht zu einem unerw"unschten Zustand f"uhren. Ich poste hier das von GTKWAVE erstellte Diagramm und dazu den Code, der nur das RS-Latch testet

library ieee;
use ieee.std_logic_1164.all;

entity meinautomat0028ausgangschaltnetz is
port
(
 a, b: in std_logic;
 x: in std_logic;
 y0, y1, y2: out std_logic
);
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinautomat0028uebergangsschaltnetz is
port
(
 a, b: in std_logic;
 aout, bout: out std_logic;
 x: in std_logic
);
end;

architecture verhalten of meinautomat0028ausgangschaltnetz is
begin
    y0 <= b;
    y1 <= a;
    y2 <= (not b and not a) or (b and a);
end;

architecture verhalten of meinautomat0028uebergangsschaltnetz is
begin
    bout <= b xor a;
    aout <= not a;
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinautomat0028rslatch is
port (
    q: out std_logic;
    r, s: in std_logic
);
end;

architecture verhalten of meinautomat0028rslatch is
    signal q1, q2 : std_logic;
begin
    q1 <= (s nor q2);
    q2 <= (r nor q1);

    q <= q1;
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinautomat0028dlatch is
port (
    q: out std_logic;
    d, c: in std_logic
);
end;

architecture verhalten of meinautomat0028dlatch is
    signal r, s, r1, s1, q1, q2 : std_logic;
begin
    s <= d;
    r <= not d;
    r1 <= r and c;
    s1 <= s and c;
    q1 <= not (r1 or q2);
    q2 <= not (s1 or q1);
    q <= q1;
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinautomat0028dmasterslaveflipflop is
port
(
    q: out std_logic;
    d, c: in std_logic
);
end;

architecture verhalten of meinautomat0028dmasterslaveflipflop is
    component meinautomat0028dlatch is
    port (
        q: out std_logic;
        d, c: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal d1: std_logic;
begin
    master: meinautomat0028dlatch PORT MAP (q=>d1, d=>d, c=>c1);
    slave: meinautomat0028dlatch PORT MAP (q=>q, d=>d1, c=>c2);
    c1 <= c;
    c2 <= not c;
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinautomat0028schaltwerk is
port
(
    c: in std_logic;
    x: in std_logic;
    y0, y1, y2: out std_logic
);
end;

architecture verhalten of meinautomat0028schaltwerk is
    component meinautomat0028dmasterslaveflipflop
    port
    (
        d, c: in std_logic;
        q: out std_logic
    );
    end component;
    component meinautomat0028ausgangschaltnetz
    port
    (
        a, b: inout std_logic;
        x: in std_logic;
        y0, y1, y2: out std_logic
    );
    end component;
    component meinautomat0028uebergangsschaltnetz
    port
    (
        aout, bout: out std_logic;
        a, b: in std_logic;
        x: in std_logic
    );
    end component;
    signal v1, v2 : std_logic;
    signal w1, w2 : std_logic;
    signal p1, p2 : std_logic;
begin
    state1: meinautomat0028dmasterslaveflipflop PORT MAP (d=>w1, c=>c, q=>v1);
    state2: meinautomat0028dmasterslaveflipflop PORT MAP (d=>w2, c=>c, q=>v2);
    ausgang: meinautomat0028ausgangschaltnetz PORT MAP (b=>v1, a=>v2, x=>x, y0=>y0, y1=>y1, y2=>y2);
    uebergang: meinautomat0028uebergangsschaltnetz PORT MAP (b=>v1, a=>v2, bout=>w1, aout=>w2,x=>x);
end;

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
    port (
        c: inout std_logic;
        x: inout std_logic;
        y0, y1, y2: out std_logic
    );
end;

library ieee;
use ieee.std_logic_1164.all;

architecture verhalten of testbench is
    component meinautomat0028rslatch
    port (
        q: out std_logic;
        r, s: in std_logic
    );
    end component;
    signal r, s, q: std_logic;
begin
    rs: meinautomat0028rslatch PORT MAP (q=>q,r=>r,s=>s);
    r <= '0' after 0 ns, '0' after 4 ns, '1' after 8 ns;
    s <= '1' after 0 ns, '0' after 4 ns, '0' after 8 ns ;
end;