Nächste Seite: Re: Aufgaben und Übungen, Aufwärts: Graphen, Schaltwerke und Zahlen Vorherige Seite: Re: Aufgaben und Übungen,
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 0
3 0 0 1 1 0
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 0
8 1 0 0 0 0
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 0
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1
1 0 0 0 1 1
9 1 0 0 1 1
10 1 0 1 0 1
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1
Gruppe 1:
1 0 0 0 1 1
Gruppe 2:
9 1 0 0 1 1
10 1 0 1 0 1
12 1 1 0 0 1
Gruppe 3:
13 1 1 0 1 1
14 1 1 1 0 1
Gruppe 4:
15 1 1 1 1 1
1:9 - 0 0 1
10:14 1 - 1 0
12:13 1 1 0 -
12:14 1 1 - 0
13:15 1 1 - 1
14:15 1 1 1 -
1:9 - 0 0 1
10:14 1 - 1 0
12:13 1 1 0 -
14:15 1 1 1 -
12:14 1 1 - 0
13:15 1 1 - 1
1:9 - 0 0 1
10:14 1 - 1 0
Gruppe 2:
12:13 1 1 0 -
Gruppe 3:
14:15 1 1 1 -
Gruppe 2:
12:14 1 1 - 0
Gruppe 3:
13:15 1 1 - 1
12:13:14:15 1 1 - -
12:14:13:15 1 1 - -
1:9 - 0 0 1
10:14 1 - 1 0
12:13:14:15 1 1 - -
12:14:13:15 1 1 - -
1:9 - 0 0 1
10:14 1 - 1 0
12:14:13:15 1 1 - -
1 9 10 12 13 14 15
1:9 * *
10:14 * *
12:14:13:15 * * * *
y <= (not x2 and not x1 and x0) or
(x3 and x1 and not x0) or
(x3 and x2);
y <= not (
(x3 or x1 or not x0) and
(not x3 or not x1 or x0) and
(not x3 or not x2)
);
library ieee;
use ieee.std_logic_1164.all;
entity meinschaltnetz0051 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture verhalten of meinschaltnetz0051 is
begin
y <= (not x2 and not x1 and x0) or
(x3 and x1 and not x0) or
(x3 and x2);
end;
library ieee;
use ieee.std_logic_1164.all;
entity meinschaltnetz0051testbench is
port (
y: out std_logic
);
end;
architecture verhalten of meinschaltnetz0051testbench is
component meinschaltnetz0051
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
sn: meinschaltnetz0051 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
0 0 0 0 0 0 1 0 0 0 1 1 2 0 0 1 0 0 3 0 0 1 1 0 4 0 1 0 0 0 5 0 1 0 1 0 6 0 1 1 0 0 7 0 1 1 1 0 8 1 0 0 0 0 9 1 0 0 1 1 10 1 0 1 0 1 11 1 0 1 1 0 12 1 1 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1
testbench: cat quine0051.txt > quine0051b.txt ./generatetestbench3 > testbench.tmp cat testbench.tmp >> quine0051b.txt echo "end;" >> quine0051b.txt cat: tail -n 50 quine0051b.txt > quine0051.vhdl compile: ghdl -a quine0051.vhdl sim: ghdl -r meinschaltnetz0051testbench --wave=wave.ghw gtkwave wave.ghw
testbench: cat quine0051.txt > quine0051b.txt ./generatetestbench3 > testbench.tmp cat testbench.tmp >> quine0051b.txt echo "end;" >> quine0051b.txt cat: tail -n 50 quine0051b.txt > quine0051.vhdl compile: ghdl -a quine0051.vhdl sim: ghdl -r meinschaltnetz0051testbench --wave=wave.ghw gtkwave wave.ghw
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 0
3 0 0 1 1 0
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 0
8 1 0 0 0 0
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 0
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1
1 0 0 0 1 1
9 1 0 0 1 1
10 1 0 1 0 1
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1
Gruppe 1:
1 0 0 0 1 1
Gruppe 2:
9 1 0 0 1 1
10 1 0 1 0 1
12 1 1 0 0 1
Gruppe 3:
13 1 1 0 1 1
14 1 1 1 0 1
Gruppe 4:
15 1 1 1 1 1
1:9 - 0 0 1
10:14 1 - 1 0
12:13 1 1 0 -
12:14 1 1 - 0
13:15 1 1 - 1
14:15 1 1 1 -
1:9 - 0 0 1
10:14 1 - 1 0
12:13 1 1 0 -
14:15 1 1 1 -
12:14 1 1 - 0
13:15 1 1 - 1
1:9 - 0 0 1
10:14 1 - 1 0
Gruppe 2:
12:13 1 1 0 -
Gruppe 3:
14:15 1 1 1 -
Gruppe 2:
12:14 1 1 - 0
Gruppe 3:
13:15 1 1 - 1
12:13:14:15 1 1 - -
12:14:13:15 1 1 - -
1:9 - 0 0 1
10:14 1 - 1 0
12:13:14:15 1 1 - -
12:14:13:15 1 1 - -
1:9 - 0 0 1
10:14 1 - 1 0
12:14:13:15 1 1 - -
1 9 10 12 13 14 15
1:9 * *
10:14 * *
12:14:13:15 * * * *
y <= (not x2 and not x1 and x0) or
(x3 and x1 and not x0) or
(x3 and x2);
y <= not (
(x3 or x1 or not x0) and
(not x3 or not x1 or x0) and
(not x3 or not x2)
);
library ieee;
use ieee.std_logic_1164.all;
entity meinschaltnetz0051 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture verhalten of meinschaltnetz0051 is
begin
y <= (not x2 and not x1 and x0) or
(x3 and x1 and not x0) or
(x3 and x2);
end;
library ieee;
use ieee.std_logic_1164.all;
entity meinschaltnetz0051testbench is
port (
y: out std_logic
);
end;
architecture verhalten of meinschaltnetz0051testbench is
component meinschaltnetz0051
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
sn: meinschaltnetz0051 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;
x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x3 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity meinschaltnetz0051 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture verhalten of meinschaltnetz0051 is
begin
y <= (not x2 and not x1 and x0) or
(x3 and x1 and not x0) or
(x3 and x2);
end;
library ieee;
use ieee.std_logic_1164.all;
entity meinschaltnetz0051testbench is
port (
y: out std_logic
);
end;
architecture verhalten of meinschaltnetz0051testbench is
component meinschaltnetz0051
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
sn: meinschaltnetz0051 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;
x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x3 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
end;