Nächste Seite: quine20241125.vhdl Aufwärts: Übungen Vorherige Seite: nasm20241125003mmx.asm
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 0
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 0
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 1
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 1
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 1
5 0 1 0 1 1
6 0 1 1 0 1
8 1 0 0 0 1
9 1 0 0 1 1
12 1 1 0 0 1
15 1 1 1 1 1
Gruppe 1:
1 0 0 0 1 1
2 0 0 1 0 1
8 1 0 0 0 1
Gruppe 2:
3 0 0 1 1 1
5 0 1 0 1 1
6 0 1 1 0 1
9 1 0 0 1 1
12 1 1 0 0 1
Gruppe 4:
15 1 1 1 1 1
1:3 0 0 - 1
1:5 0 - 0 1
1:9 - 0 0 1
2:3 0 0 1 -
2:6 0 - 1 0
8:9 1 0 0 -
8:12 1 - 0 0
15 1 1 1 1
2:3 0 0 1 -
8:9 1 0 0 -
1:3 0 0 - 1
1:5 0 - 0 1
2:6 0 - 1 0
8:12 1 - 0 0
1:9 - 0 0 1
15 1 1 1 1
Gruppe 1:
2:3 0 0 1 -
8:9 1 0 0 -
1:3 0 0 - 1
Gruppe 1:
1:5 0 - 0 1
2:6 0 - 1 0
8:12 1 - 0 0
1:9 - 0 0 1
15 1 1 1 1
1 2 3 5 6 8 9 12 15
2:3 + +
8:9 + +
1:3 + +
1:5 + +
2:6 + +
8:12 + +
1:9 + +
15 +
1 2 3 5 6 8 9 12 15
2:3 + +
8:9 + +
1:3 + +
1:5 + + p
2:6 + + p
8:12 + + p
1:9 + +
15 + p
1 2 3 5 6 8 9 12 15
1:3 + + p
1:5 + + p
2:6 + + p
8:12 + + p
1:9 + + p
15 + p
1:3 0 0 - 1
1:5 0 - 0 1
2:6 0 - 1 0
8:12 1 - 0 0
1:9 - 0 0 1
15 1 1 1 1
Disjunktive Normalform:
y <= (not x3 and not x2 and x0) or
(not x3 and not x1 and x0) or
(not x3 and x1 and not x0) or
(x3 and not x1 and not x0) or
(not x2 and not x1 and x0) or
(x3 and x2 and x1 and x0);
Konjunktive Normalform:
y <= not (
(x3 or x2 or not x0) and
(x3 or x1 or not x0) and
(x3 or not x1 or x0) and
(not x3 or x1 or x0) and
(x2 or x1 or not x0) and
(not x3 or not x2 or not x1 or not x0)
);
library ieee;
use ieee.std_logic_1164.all;
entity quine20241125 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20241125 is
begin
y <= (not x3 and not x2 and x0) or
(not x3 and not x1 and x0) or
(not x3 and x1 and not x0) or
(x3 and not x1 and not x0) or
(not x2 and not x1 and x0) or
(x3 and x2 and x1 and x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20241125testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20241125testbench is
component quine20241125
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20241125 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
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