dlatch20241130.vhdl

-- (C) David Vajda
-- 2024-11-30
-- VHDL - RS-Latch .. D-Latch .. D-Flip Flop

library ieee;
use ieee.std_logic_1164.all;

entity rslatch20241130 is
port (
    r: in std_logic;
    s: in std_logic;
    q: inout std_logic;
    p: inout std_logic
);
end;

architecture behaviour of rslatch20241130 is
begin
    q <= (r nor p);
    p <= (s nor q);
end;

library ieee;
use ieee.std_logic_1164.all;

entity clkrslatch20241130 is
port (
    r: in std_logic;
    s: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of clkrslatch20241130 is
    component rslatch20241130
    port (
        r: in std_logic;
        s: in std_logic;
        q: inout std_logic;
        p: inout std_logic
    );
    end component;
    signal e, f: std_logic;
begin
    rs: rslatch20241130 PORT MAP (r=>e, s=>f, q=>q);
    f <= r and c;
    e <= s and c;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatch20241130 is
port (
    c: in std_logic;
    d: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dlatch20241130 is
    component clkrslatch20241130
    port (
        r: in std_logic;
        s: in std_logic;
        c: in std_logic;
        q: inout std_logic
    );
    end component;
    signal e, f: std_logic;
begin
    clkrs: clkrslatch20241130 PORT MAP (s=>e, r=>f, c=>c, q=>q);

    e <= d;
    f <= not d;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dff20241130 is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dff20241130 is
    component dlatch20241130
    port (
        d: in std_logic;
        c: in std_logic;
        q: inout std_logic
    );
    end component;
    signal e, f, x: std_logic;
begin
    d2: dlatch20241130 PORT MAP (c=>f, q=>q, d=>x);
    d1: dlatch20241130 PORT MAP (c=>e, d=>d, q=>x);
    f <= not c;
    e <= c;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dff20241130testbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dff20241130testbench is
    component dff20241130
    port (
        d: in std_logic;
        c: in std_logic;
        q: inout std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dff: dff20241130 PORT MAP (d=>d, c=>c, q=>q);

-- diesen Teil habe ich aus dem Alten uebernommen


    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;