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y <= (not x3 and not x2 and not x1 and not x0) or
(not x3 and x1 and x0) or
(x3 and not x1 and x0) or
(x3 and x2 and x1);
y <= not (
(x3 or x2 or x1 or x0) and
(x3 or not x1 or not x0) and
(not x3 or x1 or not x0) and
(not x3 or not x2 or not x1)
);
library ieee;
use ieee.std_logic_1164.all;
entity quine20241109 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20241109 is
begin
y <= not (
(x3 or x2 or x1 or x0) and
(x3 or not x1 or not x0) and
(not x3 or x1 or not x0) and
(not x3 or not x2 or not x1)
);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20241109_testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20241109_testbench is
component quine20241109
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20241109 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
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library ieee;
use ieee.std_logic_1164.all;
entity rslatch20241109 is
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
qs: inout std_logic
);
end;
architecture behaviour of rslatch20241109 is
begin
q <= (r nor qs);
qs <= (s nor q);
end;
library ieee;
use ieee.std_logic_1164.all;
entity rslatch20241109testbench is
port (
q: inout std_logic
);
end;
architecture behaviour of rslatch20241109testbench is
component rslatch20241109
port (
r: in std_logic;
s: in std_logic;
q: inout std_logic;
qs: inout std_logic
);
end component;
signal r, s: std_logic;
begin
rs: rslatch20241109 PORT MAP (r=>r, s=>s, q=>q);
r <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns;
s <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns;
end;
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