RS-Latch, 2024-11-17

library ieee;
use ieee.std_logic_1164.all;

entity rslatch20241117 is
port (
    r: in std_logic;
    s: in std_logic;
    q: inout std_logic;
    p: inout std_logic
);
end;

architecture behaviour of rslatch20241117 is
begin
    q <= r nor p;
    p <= s nor q;
end;

library ieee;
use ieee.std_logic_1164.all;

entity rslatch20241117testbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of rslatch20241117testbench is
    component rslatch20241117
    port (
        r: in std_logic;
        s: in std_logic;
        q: inout std_logic;
        p: inout std_logic
    );
    end component;
    signal r, s: std_logic;
begin
    rs: rslatch20241117 PORT MAP (r=>r, s=>s, q=>q);

    r <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns;
    s <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '0' after 50 ns, '0' after 60 ns;
end;