2024-11-18, D-Latch

library ieee;
use ieee.std_logic_1164.all;

entity rslatch20241118 is
port (
    r: in std_logic;
    s: in std_logic;
    q: inout std_logic;
    p: inout std_logic
);
end;

architecture behaviour of rslatch20241118 is
begin
    q <= (r nor p);
    p <= (s nor q);
end;

library ieee;
use ieee.std_logic_1164.all;

entity rslatch20241118testbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of rslatch20241118testbench is
    component rslatch20241118
    port (
        r: in std_logic;
        s: in std_logic;
        q: inout std_logic;
        p: inout std_logic
    );
    end component;
    signal r, s: std_logic;
begin
    rs: rslatch20241118 PORT MAP (r=>r, s=>s, q=>q);

    -- hineinkopiert

    r <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns;
    s <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '0' after 50 ns, '0' after 60 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity clktriggerdrslatch20241118 is
port (
    q: inout std_logic;
    r: in std_logic;
    s: in std_logic;
    c: in std_logic
);
end;

architecture behaviour of clktriggerdrslatch20241118 is
    component rslatch20241118
    port (
        r: in std_logic;
        s: in std_logic;
        q: inout std_logic;
        p: inout std_logic
    );
    end component;
    signal rc, sc: std_logic;
begin
    rs: rslatch20241118 PORT MAP (r=>rc, s=>sc, q=>q);
    rc <= r and c;
    sc <= s and c;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatch20241118 is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dlatch20241118 is
    component clktriggerdrslatch20241118
    port (
        q: inout std_logic;
        r: in std_logic;
        s: in std_logic;
        c: in std_logic
    );
    end component;
    signal dr, ds: std_logic;
begin
    dl: clktriggerdrslatch20241118 PORT MAP (r=>dr, s=>ds, c=>c, q=>q);
    dr <= d;
    ds <= not d;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatch20241118testbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dlatch20241118testbench is
    component dlatch20241118
    port (
        d: in std_logic;
        c: in std_logic;
        q: inout std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dlatch20241118 PORT MAP (d=>d, c=>c, q=>q);

    d <= '0' after 0 ns, '1' after 20 ns,  '0' after 30 ns, '1' after 40 ns, '1' after 50 ns,  '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '0' after 150 ns;
    c <= '0' after 0 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '0' after 70 ns, '1' after 100 ns, '0' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '0' after 170 ns;
end;