Re: VHDL

-- 0001 VHDL - Multiplexer, Adder, Fulladder, Paralleladder, Coder, Decoder
-- without architecture and entity - this will be in 0002 - VHDL

-- Multiplexer

    signal a: bit_vector (3 downto 0);
    signal b: bit_vector (3 downto 0);
    signal c: bit_vector (3 downto 0);

    process (cout)
    begin
        a <= ain;
        b <= bin;
        if (clk='0') then
            c <= a;
        elseif (clk='1') then
            c <= b;
        end if;
        cout <= c;
    end process;